Linda Wang
Sunnyvale, CA 94087
Email: 
Tel:  [Send email to request phone number] 10-8548
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Objective: Seeking a Sr. Engineering/Management position of Device Reliability,
Quality Engineering with an aggressive organization that promotes creativity,
quality and innovative solutions 

SUMMARY

Over 10 years experience on semiconductor process, reliability, quality
engineering and device physics. 

Project Management Experience, experience to train engineers on reliability,
quality, failure analysis and device modeling. Experience to manage reliability
labs and lab staffs.

Expert on NPI Product Qualification and Reliability test, Quality System audit
and subcontractor management. Expert on product reliability qualification,
failure analysis and wafer level reliability.

Strong background in device physics, semiconductor device characterization and
modeling. Solid background in semiconductor material and integrated circuits
fabrication process. Experience on testline structure design and layout, DRC
caliber check, SPICE model on BSIM4.

Expert on wafer level reliability and process evaluation of TDDB, Qbd, Stress
Migration, electromigration, hot carrier injection HCI, NBTI, PBTI, Vt stability,
Beta degradation tests on the process of BiCMOS, Bipolar and CMOS 0.13um and
0.18um process. Good knowledge on high voltage MOS and DMOS devices.

Experience to work on flash memory and EEPROM process development, qualification
and reliability test. Expert on EEPROM retention test, disturb test, program
/erase cycling tests for tunneling oxide and HV oxide integrity test. Expert on
ASIC, SoC, and analog product reliability qualification, wafer level reliability
qualification and process evaluation. Familiar with JEDEC, MIL-Std-883, etc.
Hands on experience and familiar with QUALITAU, KEITHLEY S4200 test system,
HP/Agilent 4145/5156   etc

Experience working with internal fab for CMOS and high voltage device, bipolar
device process development, qualification test and design rule setup. Experience
working with TSMC, SMIC, and UMC foundry on process reliability qualification
test in fabless style environment. 

Expert in failure analysis techniques and practical experience with IC process,
and assembly related failure analysis, e.g., SEM, TEM, EDX, X-section, CSAM,
liquid crystal, emission scope, etc.

Practical experience on IC assembly and package manufacturing process control.
Strong practical and theoretical skills in FMEA, SPC and DOE. 

Certified reliability engineer (CRE) training (under ASQ). Expertise on product
reliability lifetime prediction (MTTF, FIT   .), new product qualification and
reliability tests. Expert in Burn-in hardware design and setup. Skillful in
detecting product quality and reliability problems and handling customer
reliability issues and corrective actions. Very familiar with JEDEC, MIL-STD-883
standards and CMOS IC layout. 

Expert in ISO9000 audit with ISO 9000 lead auditor training. Experience in
quality assurance, quality system management audit and manufacturing process
control audit within internal production, supplier and subcontractor site. 

Strong project management skills. Good team worker, good communication skills.
Self-motivated.

QUALIFICATIONS

DEVICE PHYSICS AND MODELING ON MEMORY DEVICE, TESTINE LAYOUT DESIGN AND
CHARACTERIZATION ON 65nm and 45nm CMOS FROM TSMC AND OTHER FOUNDRY.
. design SRAM and Flash memory testchip layout, BSIM3 modeling and simulation.
. testchip characterization, final mask jobview after tapeout
. SPICE model check in and release from foundry

WAFER LEVEL RELIABILITY EVALUATION on CMOS 0.18um, CMOS 0.13um, CMOS 90nm,
BiCMOS, BIPOLAR, PROCESS, YIELD ENHANCEMENT, PROCESS INTEGRATION, DEVICE PHYSICS
  Expert on wafer level reliability evaluation e.g. TDDB, HCl, EM, NBTI, Vt
stability, Beta stability on CMOS, BICMOS and bipolar device process
  experience on Cu interconnect technology and process integration (including
stress migration test)
  very familiar with semiconductor processes (e.g., implant, deposition, etch,
lithography)
  good understanding of IC layout, DRC, gate oxide reliability, deep sub-micron
transistor device physics.
  Work with TSMC on low-K process, CMOS 0.18um 1P6M logic process integration
and 
reliability qualification

ASIC, SOC, ANALOG/DIGITAL DEVICE and FLASH MEMORY DEVICE QUALIFICATION AND
RELIABILITY TEST:
* expertise in detecting potential quality and reliability problems in the area
of product design, IC processes and package control for semiconductor devices. 
* expertise in new SoC product qualification, failure analysis and reliability
test program setup, and reliability burn-in circuit design
* experience in flash memory, EEPROM memory reliability qualification test
* expertise in product reliability lifetime prediction, failure rate prediction
of MTTF, FIT, 
* capable of multi-tasking, providing good leadership and support work with
purchasing, materials, engineering, R*D and manufacturing groups handling
customer complaints and corrective action reports. 

IC PACKAGE RELIABILITY AND PROCESS CONTROL
* expert on IC package characterization and failure analysis, e.g., PCB process,
SMT
* very familiar with IC package front-end and back-end process control including
ball shear, wire pull, die shear/die attach, molding, casting, lead frame
deflashing...

EXPERIENCE IN FAILURE ANALYSIS
* familiar with failure analysis techniques that includes encapsulation mound
compound, material analysis, die attach, ball shear, wire pull test, X-ray, CSAM
delamination test, SMT back end process, PCB defect, IC process defect by the
methods of X-ray, SEM, EDX, DSC, Tg, TGA, FIB and CSAM delamination check.

EXPERIENCE ON FIBER OPTICS PASSIVE COMPONENTS AND AMPLIFIERS RELIABILITY
* experience working on infrared and fiber optics transceiver, passive
components and optical amplifiers EDFA
* familiar with Bellcore standards GR-1312, GR-1221. Familiar with Agilent test
and measurement equipment

QUALITY SYSTEM MANAGEMENT, QUALITY ASSURANCE AND AUDIT:
* familiar with ISO-9000/9001 standards, FMEA , SPC and DOE
* expertise in conducting ISO9000/9001, quality system management evaluation and
audit to material supplier, internal manufacturer and subcontractors in various
countries 
* expertise in conducting manufacturing process control audit, work to ensure
engineering specification and standards compliance for semiconductor device
manufacturing
* skillful at product yield data gathering and analyzing, root cause analysis,
rework/disposition procedure/criteria setup

PROFESSIONAL EXPERIENCE

Mar. 2007  *  now, Monolithetic System Inc, Sunnyvale, CA. Sr. Device
Reliability Engineer/Project Lead

  work on device reliability and qualification test on CMOSHV process from
foundry umc & tsmc0.13um 90nm, 65nm process 
  Lead projecs on UMC, TSMC, SMIC, NEC prototype design and verification on
memory products
  design testline structure from layout till tapeout. Conduct characterization
of prototype reliability and qualification on memory product and mix-signal
product
  run DRC check, SPICE modeling of BSIM4 based on foundry  's tech library

2006- 2007, Staff Quality Engineer, Telegent System, Sunnyvale, CA
work on quality system setup, reliability program setup, NPI program setup,
quality system audit to vendor setup 

2002- 2006, Sr Member of Technical Staff/project leader, Maxim Integrated
Products, Sunnyvale CA 

  work on wafer level reliability and process development reliability of BiCMOS,
CMOS, bipolar process on test chips and products. Work with process TRD for
electrical design rule setup, modeling, flash memory process development.
  Project leader on EEPROM device reliability qualification, burn-in setup, test
spec execution, coordinate with design, test, product, production and QA team to
keep projects moving on target, release the product on time.
  Giving training to junior engineers.
  work on product level reliability qualification on both logic and analog
devices, e.g., HVNMOS, DMOS, flash EEPROM devices. Work with internal purchasing
and outside vendors on material supply changes on IC fabrication process and
assembly process. Issue Reliability Qualification Report to release new
products.
  Work on the oxide reliability tests, hot carrier lifetime projection test, and
metal migration test on CMOS 0.13um, 0.18um. Also, NBTI on PMOS, Beta stability
on NPN, PNP transistors. Those tests include TDDB, Qbd, stress migration, EM,
HCL, NBTI, PBTI, Vt stability, and Beta Degradation.
  Initiate failure analysis on qualification failures.
  Review PT data and wafer yield analysis on all kinds of processes like CMOS,
BiCMOS, Flash.

2001---2002, Sr. Reliability Engineer, LSI Logic Milpitas, CA
  work on process modeling, wafer level reliability test and evaluation for CMOS
0.18um device
  work with TSMC and UMC foundry on yield enhancement for CMOS 0.18um SoC
device
  work on CMOS 0.13um Cu technology, process evaluation, and DRC
  work with internal fab on process integration, yield analysis, reliability
qualification

1997- 2001 Quality and Reliability Engineer
Agilent Technologies Pte Ltd, (former Hewlett-Packard Pte Ltd), Singapore
* work on IR transceiver device reliability evaluation, process control and
yield analysis
* manage the reliability lab technision and operators.
* work on infrared and fiber optics transceiver IC assembly and package process
control and reliability test
* set-up and develop reliability test program for new product qualification and
evaluation, design and set-up burn-in board and system for new product
reliability test
* conduct regular reliability test for on-going products reliability monitor, to
detect and solve potential quality and reliability problems for on-going
products, perform failure analysis for defective products, provide qualification
report to customer
* conduct regular IS