Sandy Metzgar
970 Mayfair Ct.
Elk Grove, Illinois 60007
[Send email using form at bottom]
 [Send email to request phone number] 15-2930

SUMMARY:  Customer-focused professional with experience in integrated circuit
design and project management. Background includes the complete product cycle
from market exploration, competitive solutions, system specification,
architecture, design, manufacturing and test. Strong track record as a top-level
performer and team player.	
	
WORK EXPERIENCE:

ATI Technologies(acquired by Advanced Micro Devices 10/06) 1/06-8/08 
Senior Program Manager for Mobile TV, Consumer Electronics Group

•Prepared, tracked and communicated project plans for all Mobile TV efforts. 
•Coordinated day-to-day development activities with product core teams in
Chicago, India and Toronto to ensure product delivery to agreed upon schedule and
cost.
•Managed WTV200 DVB-T/H ASIC tapeout, software development, functional
verification and qualification efforts to meet customer technical and schedule
requirements. This DVB-T/H design has patented algorithms for optimal receiver
performance in a mobile environment, exceeding the MBRAI2 mobile and portable
radio access specification for DVB-T/H.

   
PrairieComm (acquired by Freescale Semiconductor 2/05)   8/00-1/06
UMTS Manager, System-on-a-Chip (SoC) Development Group (PrairieComm)

•Demonstrated strong organizational, scheduling, communication and technical
skills to lead a cross-functional team of 25+ front-end design, back-end design,
systems and product engineers to design and build a fully functional
UMTS/GSM/GPRS 5110 chip in less than 9 months using a COT flow. This 5110-CS1
chip satisfied our customer’s requirements for making UMTS and GSM calls, and
gave PrairieComm credibility in the 3G market. The second generation 5110-CS2
chip added several features and was capable of simultaneous 384 kbps Tx/Rx
performance. Both chips achieved first pass success and were fully documented
with a 500+ page ASSP specification. 
•Assumed the Manufacturing Manager role coordinating and achieving close to 100%
on-time customer delivery through communication with PrairieComm sales team,
foundry, assembly and test suppliers. Responsibilities included monthly forecasts
to suppliers based on sales projections, working with customers to achieve
correlation of SoC production test and handset production test, and weekly
manufacturing reports.

L1 Senior Program Manager (Freescale Wireless Mobile Systems Group)

•Project coordination for three L1 software programs including resource
analysis, Microsoft Project schedules, PERT charts, risk mitigation and customer
support.


VLSI Technology (Philips Semiconductors subsidiary 1999) 11/94-8/00             

Corporate Reuse Coordinator, Strategic Technology

•Defined and implemented VLSI intellectual property (IP) reuse strategy
including a logistical description of how to get IP into HDL Integrator,
checklists for reuse readiness, and bundling/licensing strategies.
•Coordinated company-wide design block reuse for VLSI and Philips development
groups with training, support, and updates to the corporate IP website.
•Demonstrated strong technical documentation skills and methodology knowledge to
describe the entire ASIC design flow process from the RTL description through
layout and verification.

Mentor Development/System Test Project Manager, Design Automation

•Managed work efforts for three individuals for development and test of Design
Integrator Mentor consisting of Mentor, Synopsys, Compass and VLSI tools.
•Demonstrated strong mathematical skills to implement the Compass ISM delay
calculation method in Design Integrator Mentor.

Motorola, Semiconductor Products Group		1/85-11/94
Principal CAE Engineer, High End MPU Semi-Custom Group 

•Technical program management of the General Instrument program consisting of
eight circuits. Provided customer support and training for CADENCE framework
standard cell design kits on Sun SPARC and HP platforms.

Section Manager, Military Product ASIC Software Development

•Managed work efforts for three individuals for creation and support of military
OACS (Open Architecture CAD System) design kits on Apollo, HP and Sun platforms.
Provided customer support for OACS design kits as in support of the Iridium
program.

CMOS Design Engineer, ASIC New Product Development and MICARL

•Technical project leader for the Unisys UYK-44 program including gate array,
standard cell and full custom circuits. Demonstrated technical and creative
hard-working efforts to meet an extremely tight schedule that saved Unisys
millions of dollars in their customer contracts.

EDUCATION:
                                                               
University of Connecticut                      B.S.E.E  May,1984    
College of Engineering:  Electrical Engineering / Double major with Metallurgy  
 GPA:  3.95/400
                                                          
Arizona State University                                                      
College of Engineering                               
Twelve hours toward MSEEE Solid-State Electronics

ACHIEVEMENTS:

•Received Q3 1998 Design Reuse Recognition Award for release of CTG analog
blocks into HDL Integrator.
•Received Motorola Sector Imperative Award in July 1990 for implementation of a
high performance 50 MHz Cache Controller design utilizing the 75% UDR HDCMOS
technology and the Corporate Cell Library.
•Co-authored a paper on the VHSIC 6K gate array circuit for the 1987 ISSCC
Conference.