OBJECTIVE 
Seeking a Full Time position. 

SUMMARY 
Hands-on experience in Xilinx 9.1i, Cadence Design tools, Basys Board, Modelsim.

Working knowledge in operating systems and extensively used UNIX. 
Dedication and drive as a hard-working individual. 
Work Experience in Hewlett Packard Globalsoft Limited.
Superlative communication and team-building skills. 

EDUCATION 
M.S. Electrical Engineering, February 2008 
Major: Microelectronics 
University at Buffalo, State University of New York 
GPA: 3.2/4.0 

B.E Electronics and Communication, Aug 2005 
University Visvesvarayya College of Engineering, Bangalore, India 
GPA: 3.75/4.0 

TECHNICAL SKILLS 
Cadence IC Design Tools: Schematic Capture Editor, Virtuoso composer,
Virtuoso-XL Layout editor,Affirma; Spice simulators:Spectre, 
Spectre-Verilog, Hspice, PSpice. 
Simulation Tools: Modelsim SE 5.5, Xilinx ISE 9.1i. 
Embedded Systems: Intel 8086 family, Intel 8085 family, Motorola 68000/6800. 
HDLs: VHDL, VERILOG. 
Software Languages: C, C++, Assembly language, Perl, MatLab, Simulink, HTML,
XML. 
Operating System: Windows (98, 2000, XP, NT), Unix, Linux, Sun Solaris. 
Application Software: MS Office (Word, Power Point, Excel, Front Page). 

WORK EXPERIENCE 
HEWLETT PACKARD GLOBAL SOFT LIMITED, Aug 05-Dec 05
Software Engineer 
HTML, XML, SDLC, Communication skills, Team work, Time Management skills. 

SUNY BUFFALO, The Research Foundation, May 2007-November 2007
UNITED STATES POSTAL SERVICE, Truther

ACADEMIC PROJECTS 
8 Bit Carry Look Ahead Adder in 130nm technology 
•Used wavepipelining technique to increase throughput of Carrylookahead Adder. 
•Understood problems like crosstalk noise, interconnect delay, signal integrity
in 130nm
•Learnt rough tuning by adding delay elements to make path difference almost
zero. 

Analysis of LNA design parameters of ATF35143 GaAs HEMT using Ansoft
•Analyzed S parameters and plotted them in the range of 0-10GHz.
•Added passive elements to improve stability and realized the performance
tradeoffs

FPGA Implementation of (Xilinx Vertex series) DGA Electronics CPU Card using
VHDL, 
ISRO, Bangalore 
•Interfaced real time Stack based processor RTX 2010 with external PROMS,
resolvers, linear controllers BU-61580 and MIL-STD 1553. 
•Calculated Angle, Azimuth, and Elevation for antenna control of the satellite.

•Coded in VHDL.Did timing analysis, Place and Route.

8 Bit Kogge Stone Adder 
•Designed and simulated Adder using cadence IC Design tools like Virtuoso
Composer, Virtuoso-XL Layout Editor and Spectre Spice simulator. 
•Laid out in AMI 0.5u technology padframe from MOSIS. 
•Simulated using Spice simulator. Used random test vectors for testing. 
•Achieved controlled fanout, regular layout in comparison to Carry Look Ahead
Adder. 

8 Bit ALU 
•Designed using Verliog in XILINX ISE 9i and simulated in Modelsim 6.0 
•Displayed results on BASYS Board Spartan 3E series. 

Matched Layout of Folded Cascode Operational Transconductance Amplifier 
•Designed and simulated circuit and layout of Operational Transconductance
Amplifier using Virtuoso Schematic Composer, 
Virtuoso Layout Editor and simulator like Affirma Spectra simulator. 
•Used layout techniques like Common Centriod, Symmetry, chirality, compactness
and dispersion. 

CMOS Differential Amplifier 
•Designed and simulated using Virtuoso Schematic editor, Magic layout editor and
Spectre3 simulator. 
•Placed in padframe.Achieved gain of 53db.Power dissipation for Amplifier was
200uW.

Analysis of  LNA design parameters of ATF35143 GaAs HEMT  using Ansoft
•Analysed S parameters and plotted them in the range of 0-10GHz.
•Added passive elements to improve stability and realized the performance
tradeoffs. 

COURSEWORK 
Analog Circuits, Introduction to VLSI,Microprocessors,Computer
Architecture,Advanced VLSI(digital),8051 Microcontroller,VLSI
Devices,Microelectronic Device Fabrication,Digital Signal Processing ,Analog
Integrated Circuit Layout,Advanced Switching Theory,High Speed Communication. 

REFERENCE
Available upon  request