ERIC C. MOLOY
1948 Harewood Place ~ Hillsboro, OR 97124
[Send email to request phone number] 53.3179 ~
PH.D. CHEMICAL / PROCESS / MATERIALS ENGINEER
Creative, intuitive research and development process engineer with extensive
experience in diverse, world-class semiconductor manufacturing and academic
research. Able to accurately evaluate and improve complex manufacturing
processes, equipment, and operations. Exceptional technical and interpersonal
communication skills. Skillfully reduces materials, inventory, and logistics
costs. Consistently meets stringent implementation and production deadlines.
Especially effective in fluid, high-pressure environments. An exemplary,
proactive team player who encourages and actively recognizes peak performance
from personnel at all levels. Uncompromising attention to detail. Known for
seizing initiatives, and devotion to corporate goals.
AREAS OF EXPERTISE
++ DUV 248 Photolithography
++ Process Development
++ High Volume Manufacturing
++ Technology Transfer
++ Preventative Maintenance
++ Troubleshooting & Root-Cause
++ DOE, DFM, FMEA, GFA
++ Six-Sigma SPC
++ MES300, PCSA, Discovery, Klarity
++ Project Management
++ Team Leadership & Mentoring
++ Inventory Control & Purchasing
++ Strategic Planning
++ Corporate Presentations
++ Design and Fabrication
++ Materials Characterization
++ CD-SEM, XRD, DSC/TGA
++ Materials Synthesis
++ Molecular Modeling
++ Computer Programming
++ Management Experience
"The quality of Eric's work is consistently high, with great attention to
detail. His knowledge and expertise were essential for me to gain knowledge of
the Clean Track tool, which made the technology transfer successful. Having
worked on a number of different projects with Eric, he has consistently proven
his ability to lead and support teams to achieve project goals."
Robert M. Morris, Process Engineer, Intel Corp.
“Eric is the only Engineer who really does recognize Technicians for their
contributions to the area. I am happy to see that someone really is watching,
and letting the right people know how we are doing.”
Brett E. Douglas, Module Technician, Intel Corp.
CAREER HIGHLIGHTS
++ Beat tool cycle-time and tool-availability goals in 15 out of 16 quarters
thru strategic planning, timely execution of maintenance procedures, and
effective trouble-shooting, root-cause investigations, and DOE.
++ Accomplished 100% excursion-free processing from both production and safety
perspectives.
++ Saved Intel $80,000 in unnecessary hardware upgrades by establishing new
tool-side supply-system pressures to eliminate resist foaming, which caused
process stops and wafer reworks.
++ Improved yield significantly in two technologies (65 and 45 nm) by developing
new defect monitors. These new monitors also improved reliability, precision,
and operational efficiency. Constructed a large, comprehensive Defect Atlas to
educate users, and to facilitate more consistent defect classifications.
++ Identified, tracked daily, and ultimately solved a chronic, process-related,
oven pressure issue stemming from heavier than expected resist out-gassing during
the bake process (platform related). This resulted in the creation of four new
Preventative Maintenance (PM) procedures, and a new Quarterly PM.
++ Optimized coater recipes with respect to resist thickness and RRC flows, and
established resist thickness sensitivities to RRC flows.
++ Optimized a developer rinse recipe for enhanced resist removal, improving
yield.
Conducted scores of scanner exposure/focus skew experiments to eliminate false
edge defects, resulting in the employment of individual tool-specific
exposure/focus parameter sets. This effort also led to improvements in x,y
intra-shot tilt controls (scanner).
++ Developed and implemented a new Test-Wafer route to remove an expensive,
non-redundant regeneration tool from the process flow. This reduced regeneration
cycle time from three days to one day, allowing for a reduction in the standing
inventory of test wafers (expensive consumables).
++ Devised, piloted, and implemented fully automated Test Wafer Tracking
functionality, improving wafer-history accuracy and reliability, improving wafer
handling efficiency.
++ Initiated, and helped to champion, the protocol of Operations Managers
reporting directly to Engineering – improving communications with the floor,
increasing operational efficiency, leading to shorter tool down-times, and
improving the quality of both verbal and written passdowns.
++ Developed and implemented new fab-wide chemical delivery and pickup
procedures to improve bottle handling efficiency and safety – these new
procedures are now in pilot in three other Oregon foundries.
++ Introduced new low-Titanium IPA wipes into the foundry. TexWipe® created a
new product (TX8691) to accommodate this request.
PROFESSIONAL EXPERIENCE
Senior Process Engineer, D1D Lithography, Intel Corporation, Hillsboro, Oregon
(2004 – 2007)
++ Lithography (DUV 248 nm) Clean Track Tool Owner (TEL Lithius and ACT12).
++ Participated in 300mm process technology development (65 and 45 nm), ramping
production to HVM levels, and technology transfer.
++ Charged with all maintenance, trouble-shooting, and root-cause investigations
of owned tools.
++ Provided daily and weekly tool reports to management.
++ Trained four sets of seed engineers from four different foundries in two
technologies.
++ Mentored 3-4 Module Technicians, meeting on a quarterly basis, and
contributing directly to their focals.
++ Delivered key presentations to multiple control and approval boards for
various projects.
++ Drafted and updated multiple Training Manuals, PM Procedures, Checklists, and
SPEC documents.
++ Evaluated and authorized requests for production process parameter changes
(Recipe Correlation Tables) to keep critical dimensions In Control.
++ Used metrology tools on a daily basis (Hitachi CD-SEM; KLA-Tencor Thin Film
Measurements, Patterned Wafer Inspections, and Unpatterned Surface Inspection;
Rudolph Thin Film Measurements; Leica Imaging).
Student Intern, Sandia National Labs, Albuquerque, New Mexico (2001 – 2002)
++ Two, three-month student summer internships studying the structure and
diffusion of radionuclide-bearing sodalite and cancrinite using Molecular
Mechanics, Molecular Dynamics, and Density Functional Theory in Cerius2 and
Materials Studio software.
Manager, Sierra-Sonorra Enterprises, Tempe, Arizona (1991 – 1999)
++ Involved with all aspects of operations and decision making, including
inventory, purchasing, quality control and staffing.
++ Supervised up to 50 employees, including recruitment, training, evaluations
and terminations.
++ Prepared quarterly and year-end P&L reports for senior management.
EDUCATION
Ph.D., Chemical Engineering, University of California at Davis (2004)
++ Minor in Materials Science.
++ Original research centered about zeolites, their synthesis, energetics,
structure, and dynamical properties using both simulation and experimental
techniques.
M.S., Chemical Engineering, University of California at Davis (2001)
++ Minor in Materials Science.
++ Established for the first time a linear relationship between formation
enthalpies and theoretical, internal surface areas for seventeen high-silica
zeolites, quartz, and cristobalite.
B.S.E., Chemical Engineering, Arizona State University (1999)
++ Minor in Materials Science.
++ Financed 90% of educational expenses working 20–30 hours per week.
++ Independent Study: The complex surface oxidation properties of InP, a III-V
semiconductor, was monitored using MIR-FTIR spectroscopy.
TECHNICAL PROFICIENCIES
Computational (selected):
++ Very proficient with Microsoft Office Suite, FrontPage, and OneNote.
++ Expert user of MES300.
++ Data mining in Klarity, PCSA, and Discovery corporate databases.
++ Expert user of molecular modeling Cerius2 (UNIX) and Materials Studio (WIN)
software, conducting simulations using Molecular Mechanics, Molecular Dynamics,
and DFT routines.
++ Expert user of Mathcad, instrumental (in part) to the creation of the Mathcad
7.01A Patch, urged to apply for an internship (MathSoft).
++ Familiar with Matlab, AspenPlus, Mathematica, Honeywell TDC 3000, CAD and
Pro/E, SAS Jump.
++ Computer programming experience in C, Pascal, Fortran, and Assembly (MOT).
Experimental (selected)
++ Ultra-sensitive drop-solution calorimetry (custom built twin-Calvet type).
++ DSC/TGA thermal analyses (Netzsch 449), XRD (Scintag, Inel), NMR
(Chemagnetics), TEM (Phillips).
++ Hydrothermal zeolite synthesis (Parr bombs, high-temp dehydration furnaces
w/custom built sample holder designed and built by Eric C Moloy).
Patents in Process
++ Oven Panel (became a TEL patent).
++ Nozzle centering device for TEL Lithius Clean Tracks.
++ Air-sensitive sample holder for ultra-sensitive high-temperature
calorimetry.
++ Air-sensitive XRD sample holders for Scintag and Inel diffractometers.
HONORS, AWARDS, AND DISTINCTIONS
++ Intel Corporation – Received two departmental awards and two recognition
awards.
++ Sandia National Labs/NM – Sole nominee of Sandia National Laboratories/NM
(USA) to attend the 54th Lindau Meeting of Nobel Laureates and Students in Lindau
Germany.
++ Jastro–Shields Research Scholarship Award in Chemical Engineering ($3000).
++ DoE Grand Challenge for Basic and Applied Research in Hydrogen Storage
(DE-PS36-03GO93013) Merit Reviewer for three Category 2 IIPS Proposals.
++ SNS–JINS Travel Award ($1100).
++ UC Davis Graduate Studies Travel Award ($1000).
++ SNS–JINS Travel Award ($1100).
++ NSF Travel Award ($1000).
++ ASU Board of Regents Scholarships ($10,000).
++ National Dean’s List Member.
Expanded Resume, Publications, Presentations, and Professional Development
available upon request.
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